RM182X Hardware Design Guide

Intended audience

This document is intended for hardware development engineers, layout engineers, technical support engineers and test engineers to help them complete the peripheral circuit design for the RK182X M.2 2280 module quickly and accurately.

Item	Content
Document version	V1.0
Applicable products	RM1820MC0 / RM1828MC0
Product version	RK182X M.2 2280 Module_V10
Completion date	2025-11-06

1. Module Overview

1.1 Introduction

The RK182X M.2 2280 Module is a high-performance AI compute co-processor module supporting 3B/7B large models (RK1820 supports 3B, RK1828 supports 7B), designed for AI inference and machine vision applications.

The module carries Rockchip's RK182X compute co-processor with up to 20TOPS@INT8 and three independent 64-bit RISC-V cores. RK182X embeds high-bandwidth on-chip DRAM — RK1820: 2.5GB, RK1828: 5GB — and supports a PCIe2.1 communication interface.

The module uses an M.2 Key M gold-finger connector and measures 22mm × 80mm.

1.2 Hardware Block Diagram

              ┌─────────────────────────────────┐
   3.3V ──────┤ BUCK/LDO                        │
              │                    ┌──────────┐ │
   12V ───────┤ VCC_IN             │ RK182X   │ │
              │                    │  SoC     │ │
   24MHz ─────┤ OSC                └────┬─────┘ │
              │                         │       │
              │  ┌──────────┐           │       │
              │  │ eMMC     │◄──────────┤       │
              │  │ (option) │           │       │
              │  └──────────┘           │       │
              │                         │       │
              │      Fan speed CTL ◄────┤       │
              │      Fan speed DET ────►│       │
              │      PCIe0 (EP/RC) ◄───►│       │
              │      NPOR / CLKREQ ◄────┤       │
              └─────────────────────────────────┘

1.3 Module Signal Description

Interface	Configuration	Note
Input power	12V and 3.3V provided by carrier board	12V/3A, 3.3V/3A
RAM	Embedded in chip	RK1820: 2.5GB; RK1828: 5GB
Communication	PCIe2.1	Default interface to HOST, supports boot

2. Carrier Board Interface

2.1 Connector Selection

The RK182X M.2 2280 module uses an M.2 Key M connector. Example part numbers:

Height	Model	Brand	Name
≥4.2mm	FM205003 Series	TXGA	FM205003 Series

Connector selection note

The part numbers above are verified on RK development boards and are for reference only; other connectors will be validated later. Confirm height and mechanical clearance when selecting your own.

2.2 Interface Signal Definition

For the connector signal definition between the RK182X M.2 2280 module and the carrier board, see the attached documents:

《RK1820 M.2 Module PinList_V1.0_20251025.xlsx》
Corresponding schematic symbol and PCB footprint: RK182X M.2 2280 Module interface schematic and PCB footprint

Key M specification

RK1820 M.2_2280 Module is designed per KEY M. Design your carrier-board gold-finger socket according to the KEY M specification.

2.3 Module Dimensions and Height

Dimension	Value
PCBA size	22mm × 80mm
Module thickness	6mm
Total length incl. gold finger	81mm
Structural reference width	25mm
Key notch position	21.75mm

3D structure

The full 3D structure drawing is in the attachment folder: 04.RK182X M.2 2280 Module 3D结构图

3. Application Diagram as Co-Processor Accelerator Card

        HOST (main SoC)                   RK182X M.2 Module
  ┌──────────────────────┐          ┌──────────────────────┐
  │                      │          │                      │
  │   PCIe RC            │◄────────►│   PCIe0 EP           │
  │                      │ PCIe2.1  │                      │
  │   PCIE0_PERSTN_M0    ├─────────►│   RESETN_IN          │
  │   PCIE0_CLKREQN_M0   ├─────────►│   PCIe CLKREQn       │
  │   PCIE0_WAKEN_M0     ├─────────►│   PCIe WAKEn         │
  │                      │          │                      │
  │   FAN_CTRL           ├─────────►│   Fan speed CTL      │
  │   FAN_SPEED          │◄─────────│   Fan speed DET      │
  │                      │          │                      │
  │   0R  ──── 3.3V      ├─────────►│   3.3V_IN            │
  │   12V                ├─────────►│   VCC_IN             │
  │                      │          │                      │
  │   SMBus / I2C        │◄────────►│   (Option)           │
  └──────────────────────┘          └──────────────────────┘

As a co-processor, the module runs PCIe in EP mode, with the HOST acting as RC to initiate enumeration.

4. Carrier Board Hardware Design

4.1 Input Power

The RK1820 M.2_2280 Module requires the carrier board to supply an additional 12V rail, so a dedicated 12V/3A supply must be implemented on the carrier board.

Rail	Specification	Provided by
12V	12V / 3A	Dedicated header on carrier board
3.3V	3.3V / 3W	M.2 socket on carrier board

RK provides a 12V cable converting to a 2.54mm pitch header, and also supplies a DC jack adapter cable so customers can use a DC plug for debugging.

Power design essentials

12V must run on its own dedicated power path — never tap the M.2 socket's 3.3V;
Reserve ≥3A margin on the 12V path and match the trace width;
There is no mandatory power sequencing, but 3.3V and 12V should come up together, or 12V slightly earlier.

4.2 Reset Control

PIN50 is the module reset input, active low, controlled by a HOST-side GPIO.

When the module communicates with the HOST over PCIe, the reset path is:

   HOST                          RK182X M.2 Module
   ┌────────────┐                ┌──────────────┐
   │ USB3.0     │                │              │
   │ PCIe RC    │◄──────────────►│ PCIe0 EP     │
   │            │                │              │
   │ PCIE PERST#├───────────────►│ RESET        │
   │ GPIO       ├───────────────►│              │
   └────────────┘                └──────────────┘

4.3 PCIe2.1

The RK182X M.2 2280 module has 2 PCIe2.1 interfaces, both supporting RC and EP modes. PCIe2.1 shares PHY resources with USB3.0.

Controller-to-PHY mapping:

Controller	PHY	Shared signals
PCIe2.1 Dual mode controller 0	Combo PHY 0	PCIe0 / USB0_SS_M0
PCIe2.1 Dual mode controller 1	Combo PHY 1	PCIe1 / USB0_SS_M1

The module communicates with the HOST through the PCIe0/USB3.0 Combo PHY, and can also talk to the main SoC over PCIe0 — PCIe0 supports Boot.

PCIe Control Signals and Connection

Control signal	Connection	Note
`PCIE_TXP/TXN`	Direct	PCIe data output (100nF cap already on module)
`PCIE_RXP/RXN`	Series 100nF (0201) cap	PCIe data input
`PCIE_REFCLKP/CLKN`	Direct	PCIe reference clock input or output
`PCIE_PERSTN_M*`	Direct	PCIe global reset input (EP mode)
		The SoC-side control signal may be replaced by a GPIO
`PCIE0_CLKREQN_M*`	Direct	PCIe reference clock request output (EP mode)
		The SoC-side control signal must use the dedicated function pin

CLKREQ note

PCIE0_CLKREQN_M* must use the dedicated function pin on the SoC side and cannot be replaced by an ordinary GPIO; whereas PCIE_PERSTN_M* can be replaced by a GPIO.

5. Thermal Design Recommendations

5.1 Module Cooling

Good thermal design is especially important for the performance, system stability and product safety of the RK182X M.2 2280 module.

The module uses active air cooling by default.

The RK1820 M.2_2280 Module fan interface is designed onto the module — the carrier board does not need extra circuitry. RK ships a fan by default, controlled via PWM:

   RK182X                    Fan
   ┌──────────┐          ┌────────┐
   │ PWM CH6  ├─────────►│ CTL    │
   │ PWM CH7  │◄─────────│ DET    │
   └──────────┘          └────────┘

Signal	Channel	Direction
Fan speed CTL	PWM CH6	Output (speed control)
Fan speed DET	PWM CH7	Input (speed detection)

5.2 Thermal Design Documentation

RK ships an active cooling fan by default which customers can use directly. If structural constraints or other requirements call for a custom cooling solution, refer to Rockchip's thermal design guide 《Rockchip RK182X M.2 Module 热设计指南》.

6. PCB Design Recommendations

6.1 High-Speed Interface PCB Design

Routing Requirements — PCIe2.1

Parameter	Requirement
Trace impedance	Differential 85ohm ± 10%
Max intra-pair skew	< 6mil
Inter-pair length matching	< 6inches
Trace length	< 6inches
Capacitor	100nF ± 20%, 0201 package recommended
Inter-pair spacing (airgap)	≥ 4× PCI-E trace width recommended
Max intra-pair skew (REFCLK)	< 12mil
Trace impedance (REFCLK)	Differential 100ohm ± 10%
PCIe-to-other-signal spacing (airgap)	≥ 5× PCI-E trace width recommended; at least 4×
Allowed via count per signal	No more than 2 recommended

PCIe routing red lines

Differential impedance 85ohm (data) / 100ohm (REFCLK), deviation must not exceed ±10%
Trace length and inter-pair matching must not exceed 6 inches
Via count must not exceed 2

7. Precautions

ESD Protection

Before unpacking and installing the board, take proper anti-static measures to avoid electrostatic discharge (ESD) damage to the hardware.
When transporting the module, always use a dedicated anti-static bag.
Hold the board by its edges; do not touch exposed metal parts to avoid ESD damage to components.
Place the board on a dry, flat surface, away from heat sources, EMI/RFI sources and EMI-sensitive equipment (e.g. medical devices).

Power Safety

The module does not support hot-plugging.
Verify that the input voltage is within the device's rated range.

Two hard prohibitions

Never hot-plug the module — this damages both the module and the carrier board;
Never exceed the rated input voltage — 12V/3A and 3.3V/3W are the design limits.

1. Module Overview​

1.1 Introduction​

1.2 Hardware Block Diagram​

1.3 Module Signal Description​

2. Carrier Board Interface​

2.1 Connector Selection​

2.2 Interface Signal Definition​

2.3 Module Dimensions and Height​

3. Application Diagram as Co-Processor Accelerator Card​

4. Carrier Board Hardware Design​

4.1 Input Power​

4.2 Reset Control​

4.3 PCIe2.1​

PCIe Control Signals and Connection​

5. Thermal Design Recommendations​

5.1 Module Cooling​

5.2 Thermal Design Documentation​

6. PCB Design Recommendations​

6.1 High-Speed Interface PCB Design​

Routing Requirements — PCIe2.1​

7. Precautions​

ESD Protection​

Power Safety​

Related Documents​